`timescale 1ns/1ns
module minus_4_tb; 
	reg[3:0] x,y;
	wire[3:0] out;
	wire CF;
	minus_4 E(.x (x),.y (y),.out(out),.CF(CF));
	initial begin
		x=1;y=1;#100;
		x=1;y=2;#100;
		x=1;y=15;#100;
	end
endmodule
